1. Field of the Invention
The present invention relates to information storage and retrieval, and more particularly to read only memory or storage systems using a variety of two terminal, bipolar devices in single device storage cells to achieve four levels of storage for each cell.
2. Background Information
As memory technology has developed over the past several decades, it has become well known to provide two dimensional arrays of storage cells each holding one data bit. In the evolution of semiconductor integrated circuits, a great deal of attention has been focused on achieving high density read only storage (ROS). As one example, systems have been proposed in which each cell in an integrated circuit array has been constituted of a single field effect transistor (FET), sometimes designated MOS or HMOS depending upon the form of the device. ROS integrated circuit memories have generally specified the state of a given cell by either including or omitting the gate connection to a particular FET. Accordingly, when that particular cell is addressed, one of two different voltage levels appears on a bit line. These voltage levels are then sensed to provide a binary signal output.
In the ever increasing effort to achieve greater storage density, there have been a variety of proposals to increase the number of different signal levels which can be stored within one cell. For example, three and four-level schemes have been disclosed which seek to increse significantly the information content for an array, with little increase in array size.
In order that the context of the present invention may be thoroughly understood and appreciated, reference may be made to the following patents and publications which disclose relevant concepts of ROS systems, particularly systems involving storage levels greater than two per cell:
______________________________________ U.S. Pat. No. 3,484,762 D. A. Meier 3,656,117 G. A. Maley et al 4,174,521 R. G. Neale 4,202,044 K. E. Beilstein, Jr. et al ______________________________________
Also reference may be made to the following publications: 1980 IEEE International Solid State Circuits Conference Digest at page 108 (entitled "THE NUMERIC DATA PROCESSOR" by Rafi Nave et al) and 1981 IEEE Solid State Circuits Conference Digest at page 116 (entitled "THE INTERFACE PROCESSOR FOR THE 32b COMPUTER" by Bayliss et al [see FIG. 1]).
The above cited Beilstein patent and the cited publications are regarded as particularly pertinent pieces of background information because they disclose or suggest four levels of storage for their particular memory cells. The Neale patent is pertinent in that it does indicate that its proposed memory cell may store various levels or states as a function of the cross sectional area of the single crystal column created in a semiconductor structure; the cross sectional area of the column being a function of the voltage applied and the duration of application during a so-called programming step, involving solid-phase epitaxial growth. This patent also notes that by proper selection of an alloy layer and of impurity conductivity type and concentration, a particular type of diode barrier can be formed.
Another reference that may be useful as background material is copending application Ser. No. 169,542, July 17, 1980, assigned to the assignee of the present application. That copending application discloses a read only storage system involving a storage matrix having a number of cells, each cell comprising a field effect transistor possessing one of three different gate configurations, said configurations including an enhancement-mode gate, a depletion-mode gate, and no gate, such that the cells are capable of producing three-level signals depending upon the gate configuration.